1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same.
2. Discussion of the Related Art
A conventional semiconductor device will be described with reference to the attached drawings. FIG. 2 is a plan view of a conventional semiconductor device and FIG. 3 is a cross-sectional view showing a structure of a conventional semiconductor device.
As shown in FIGS. 2 and 3, a field region and an active region are defined in a semiconductor substrate 1 and a field oxide layer 2 is formed on the field region. A gate electrode 4 having a gate oxide layer 3 is formed on the active region. A sidewall spacer 7 having a predetermined thickness is formed on both sides of the gate electrode 4. Lightly doped impurity regions 6 are formed beneath surface of the semiconductor substrate 1 both sides of the gate electrode 4. Source and drain regions 8 are formed beneath the surface of the semiconductor substrate 1, but not under the gate electrode 4 and the sidewall spacer 7.
When a semiconductor device having the foregoing structure is applied to access transistors of an SRAM cell, the operation will be described in detail with reference to FIG. 1.
The operation of writing a data "1" in a first cell node CN1 will be described. When 5 V is applied to a word line, first and second access transistors TA1 and TA2 are turned on. Subsequently, 5 V is applied to a bitline and another 5 V is applied to a bit bar line. Accordingly, data "1" and "0" are written in the first cell node CN1 and the second cell node CN2, respectively. Thus, a second drive transistor TD2 is turned on and a first drive transistor TD1 off.
The operation of reading a data "0" in the SRAM cell will be described. First of all, 5 V is applied to each of the bitline and the bit bar line. At this time, there is no current flow along the first access transistor TA1 between the bitline and the first cell node CN1 in which data "1" has been written. In contrast, current flows from the bit bar line to the second cell node CN2 along the second access transistor TA2 due to voltage difference between the bit bar line and the second cell node CN2 in which data "0" has been written. At this time, the current flowing along the second access transistor TA2 flows along the second drive transistor abruptly so that the low data written in the second cell node CN2 comes to being read.
However, the conventional, aforementioned semiconductor device has problems. When a conventional semiconductor device is applied to access transistors of an SRAM cell, on reading data "0" stored in a cell node, the current driving power of access transistors is increased and thus current flows to a second drive transistor to read data "0". As a result, the total current driving ratio is declined so that data "0" can not be exactly read, Whereby the performance of the SRAM cell becomes inferior.